SH7055S Datasheet, PDF (449/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input
Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt
status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is set by input capture
(ICR0A to ICR0D) or compare-match (CYLR6A to CYLR6D, CYLR7A to CYLR7D), clearing
by the DMAC has priority and the interrupt status flag is not set.
The timing in this case is shown in figure 11.69.
Pø
DMAC clear request
signal
Interrupt status flag
clear signal
Input capture/
compare-match signal
Interrupt status flag
ICF0A to ICF0D,
CMF6A to CMF6D,
CMF7A to CMF7D
Figure 11.69 Contention between Interrupt Status Flag Clearing by DMAC and Setting by
Input Capture/Compare-Match
Rev.2.0, 07/03, page 411 of 960