SH7055S Datasheet, PDF (894/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

24.4 Software Standby Mode
24.4.1 Transition to Software Standby Mode
To enter software standby mode, set the software standby bit (SSBY) to 1 in SBYCR, then
execute the SLEEP instruction. The SH7055SF switches from the program execution state to
software standby mode. In software standby mode, power consumption is greatly reduced by
halting not only the CPU, but the clock and on-chip peripheral modules as well. CPU register
contents and on-chip RAM data are held as long as the prescribed voltages are applied (when the
RAME bit in SYSCR is 0). The register contents of some on-chip peripheral modules are
initialized, but some are not. For details on the register states, refer to appendix A.2, Register
States in Reset and Power-Down States. The I/O port state can be selected as held or high
impedance by the port high impedance bit (HIZ) in SBYCR. For other pin states, refer to appendix
B, Pin States.
24.4.2 Canceling Software Standby Mode
Software standby mode is canceled by an NMI interrupt or a power-on reset.
Cancellation by NMI: Clock oscillation starts when a rising edge or falling edge (selected by the
NMI edge select bit (NMIE) in the interrupt control register (ICR) of the INTC) is detected in the
NMI signal. This clock is supplied only to the oscillation settling counter which counts the
oscillation stablizing time.
The oscillation settling counter overflows when it counts 2¹⁶=65536 with the input clock
frequency. Since the frequency of this counting clock is unstable until the PLL multiply curcuit is
locked in the absolute time is not fixed, and the CK pin signal output is in the high level for the
meantime.
Counting the oscillation settling time by the oscillation settling counter is used to indicate that the
clock has stabilized, so the clock is supplied to the entire chip, software standby mode is canceled,
and NMI exception processing begins.
When canceling standby mode with an NMI pin set for falling edge, be sure that the NMI pin level
upon entering software standby (when the clock is halted) is high, and that the NMI pin level upon
returning from software standby (when the clock starts after oscillation stabilization) is low. When
canceling software standby mode with an NMI pin set for rising edge, be sure that the NMI pin
level upon entering software standby (when the clock is halted) is low, and that the NMI pin level
upon returning from software standby (when the clock starts after oscillation stabilization) is high.
Cancellation by Power-On Reset: A power-on reset of the SH7055SF caused by driving the RES
pin low cancels software standby mode.
Rev.2.0, 07/03, page 856 of 960