SH7055S Datasheet, PDF (447/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If
an event such as input capture/compare-match or overflow/underflow occurs in the T2 state of an
interrupt status flag 0 write cycle by the CPU, clearing by the 0 write has priority and the interrupt
status flag is cleared.
The timing in this case is shown in figure 11.67.
TSR write cycle
T1
T2
Pø
Address
Internal write signal
TCNT
TSR address
0 written
to TSR
N
N+1
GR
N
Compare-match signal
Interrupt status flag
IMF
Figure 11.67 Contention between Interrupt Status Flag Setting by Compare-Match and
Clearing
Rev.2.0, 07/03, page 409 of 960