SH7055S Datasheet, PDF (261/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2 Register Descriptions
11.2.1 Timer Start Registers (TSTR)
The timer start registers (TSTR) are 8-bit registers. The ATU-II has three TSTR registers.
Channel
0, 1, 2, 3, 4, 5, 10
6, 7
11
Abbreviation
TSTR1
TSTR2
TSTR3
Function
Free-running counter operation/stop setting
Timer Start Register 1 (TSTR1)
Bit: 7
6
STR10 STR5
Initial value: 0
0
R/W: R/W R/W
5
STR4
0
R/W
4
STR3
0
R/W
3
STR1B,
2B
0
R/W
2
STR2A
0
R/W
1
STR1A
0
R/W
0
STR0
0
R/W
TSTR1 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT)
in channels 0 to 5 and 10.
TSTR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 7—Counter Start 10 (STR10): Starts and stops channel 10 counters (TCNT10A, 10C, 10D,
10E, 10F, and 10G). TCNT10B and 10H are not stopped.
Bit 7: STR10
0
1
Description
TCNT10 is halted
TCNT10 counts
(Initial value)
• Bit 6—Counter Start 5 (STR5): Starts and stops free-running counter 5 (TCNT5).
Bit 6: STR5
0
1
Description
TCNT5 is halted
TCNT5 counts
(Initial value)
Rev.2.0, 07/03, page 223 of 960