SH7055S Datasheet, PDF (213/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle,
and written to the transfer destination during the write cycle, so transfer is conducted in two bus
cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external
memory transfer shown in figure 10.3, data is read from one of the memories by the DMAC
during a read cycle, then written to the other external memory during the subsequent write cycle.
Figure 10.4 shows the timing for this operation.
1st bus cycle
DMAC
SAR
DAR
Data buffer
Memory
Transfer source
module
Transfer destination
module
The SAR value is taken as the address, and data is read from the transfer source
module and stored temporarily in the DMAC.
2nd bus cycle
DMAC
SAR
DAR
Data buffer
Memory
Transfer source
module
Transfer destination
module
The DAR value is taken as the address, and data stored in the DMAC's data
buffer is written to the transfer destination module.
Figure 10.3 Direct Address Operation in Dual Address Mode
Rev.2.0, 07/03, page 175 of 960