SH7055S Datasheet, PDF (455/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

External Output Value in Software Standby Mode: In software standby mode, the ATU
register and external output values are cleared to 0. However, while the channel 1, 2, and 11
TIO1A to TIO1H, TIO2A to TIO2H, TIO11A, and TIO11B external output values are cleared to 0
immediately after software standby mode is exited, other external output values and all registers
are cleared to 0 immediately after a transition to software standby mode.
Also, when pin output is inverted by the pin function controller's port B invert register (PBIR) or
port K invert register (PKIR), the corresponding pins are set to 1.
CK
TIO1A to 1H,
TIO2A to 2H,
TIO11A, 11B
Other external
outputs
Software standby mode
Figure 11.74 External Output Value Transition Points in Relation to Software Standby
Mode
Contention between TCNT Clearing from Channel 10 and TCNT Overflow: When a channel
1 or 2 free-running counter (TCNT1A, TCNT1B, TCNT2A, TCNT2B) overflows, it is cleared to
H'0000. If a clear signal from the channel 10 correction counter clear register (TCCLR) is input at
the same time, setting 1 to the overflow interrupt status flag (OVF) due to the overflow is still
performed in the same way as for a normal overflow.
Contention between Channel 10 Reload Register Transfer Timing and Write: If there is
contention between a multiplied-output transfer from the input capture register (ICR10A) to the
channel 10 reload register (RLDR10C), and the timing of a CPU write to that register, the CPU
write has priority and the multiplied output is ignored.
Contention between Channel 10 Reload Timing and Write to TCNT10C: If there is contention
between a multiplied-output transfer from the input capture register (ICR10A) to the channel 10
reload register (RLDR10C), and a CPU write to the reload counter (TCNT10C), the CPU write
has priority and the multiplied output is ignored.
Rev.2.0, 07/03, page 417 of 960