SH7055S Datasheet, PDF (833/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• The NMI, UBC, or H-UDI interrupt processing is started. Processing proceeds up to the
point where SR and PC are saved, the vector is fetched, and the start instruction of the
interrupt processing routine is fetched.
• At this point, the SCO download request with a higher priority occurs. The SCO
download processing is started.
• After the download processing has ended, the interrupt processing routine (e.g. NMI)
that was in the middle of execution resumes from the point of fetching the start
instruction of the interrupt processing routine.
• The interrupt processing routine is ended, and execution returns to the main processing.
 IRQ and on-chip peripheral module interrupt requests
Operation for when these interrupts conflict with the SCO download request is described
below.
Main processing
Contention between
SCO and interrupt
SCO download
processing
Interrupt processing,
e.g. IRQ
Figure 22.23 Contention between Interrupts (e.g. IRQ)
• An IRQ interrupt or interrupt from an on-chip peripheral module is replaced with the
SCO download request and download is executed.
• If the IRQ or on-chip peripheral module interrupt is still being requested when the
download processing has ended, the interrupt processing is executed. If these interrupt
requests have been canceled, execution returns to the main processing.
• An interrupt request is canceled when the IRQ signal, for which low-level detection is
set, has been driven high before download ends. Also refer to the description below (3.
Interrupt requests generated during download).
3. Interrupt requests generated during download
Rev.2.0, 07/03, page 795 of 960