SH7055S Datasheet, PDF (595/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.3.2 Initialization after a Hardware Reset
After a hardware reset, the following initialization processing should be carried out:
1. Clearing of IRR0 bit in interrupt register (IRR)
2. HCAN pin port settings
3. Bit rate setting
4. Mailbox transmit/receive settings
5. Mailbox (buffer) initialization
6. Message transmission method setting
These initial settings must be made while the HCAN is in bit configuration mode. Configuration
mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and
the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is
exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN
automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up
sequence then begins, and communication with the CAN bus is possible as soon as the sequence
ends. The power-up sequence consists of the detection of 11 consecutive recessive bits.
IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery
from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are
enabled, IRR0 should be cleared.
HCAN Pin Port Settings: HCAN pin port settings must be made during or before bit
configuration. Refer to the section 20, Pin Function Controller (PFC), for details of the setting
method.
The SH7055SF has two on-chip HCAN channels, which can be used in either of the following
ways:
1. Two-channel 16-buffer HCAN
2. One-channel 32-buffer HCAN
An example of 2-channel/16-buffer independent use is shown in figure 16.7, and an example of 2-
channel/32-buffer use in figure 16.8.
Rev.2.0, 07/03, page 557 of 960