SH7055S Datasheet, PDF (884/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

23.2 Operation
The on-chip RAM is controlled by means of the system control register (SYSCR).
When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Accesses to addresses
H'FFFF6000–H'FFFFDFFF are then directed to the on-chip RAM.
When the RAME bit in SYSCR is cleared to 0, the on-chip RAM is not accessed. A read will
return an undefined value, and a write is invalid. If a transition is made to hardware standby mode
after the RAME bit in SYSCR is cleared to 0, the contents of the on-chip RAM are held.
For details of SYSCR, see 24.2.2, System Control Register (SYSCR), in section 24, Power-Down
State.
Rev.2.0, 07/03, page 846 of 960