SH7055S Datasheet, PDF (421/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10–13
in free-running counter TCNT0L with bit ITVE0–ITVE3 in the interval interrupt request register
(ITVRR), the IIF bit is set to 1 in the timer status register (TSR).
The timing in this case is shown in figure 11.41. TCNT0 value N in the figure is the counter value
when TCNT0L bit 6–13 changes to 1. (For example, N = H'00000400 in the case of bit 10,
H'00000800 in the case of bit 11, etc.)
CK
TCNT input clock
TCNT0
N–1
N
Internal interval signal
Interrupt status flag
IIF
Interrupt request signal
Figure 11.41 Timing of IIF Setting Timing by Interval Timer
Rev.2.0, 07/03, page 383 of 960