SH7055S Datasheet, PDF (189/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

9.3.3 CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the RD, WRH, or WRL signal assert period
beyond the length of the CSn signal assert period by setting the SW3–SW0 bits of BCR2. This
allows for flexible interfaces with external circuitry. The timing is shown in figure 9.6. T_h and T_f
cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these
cycles; RD, WRH, and WRL signals are not. Further, data is extended up to the T_f cycle, which is
effective for gate arrays and the like, which have slower write operations.
T_h
CK
T₁
T₂
T_f
Address
Read
Write
Data
,
Data
Figure 9.6 CS Assert Period Extension Function
Rev.2.0, 07/03, page 151 of 960