SH7055S Datasheet, PDF (187/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

9.3.2 Wait State Control
The number of wait states inserted into external space access states can be controlled using the
WCR settings (figure 9.4). The specified number of T_W cycles are inserted as software cycles at
the timing shown in figure 9.4.
T₁
T_W
T₂
CK
Address
Read
Data
Write
,
Data
Figure 9.4 Wait State Timing of External Space Access (Software Wait Only)
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