SH7055S Datasheet, PDF (795/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

(2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU)
This parameter sets the operating frequency of the CPU.
For the range of the operating frequency of this LSI, see section 25.3.2, Clock Timing.
Bit :
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit :
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Bit :
15
14
13
12
11
10
9
8
F15
F14
F13
F12
F11
F10
F9
F8
Bit :
7
6
5
4
3
2
1
0
F7
F6
F5
F4
F3
F2
F1
F0
Bits 31 to 16—Unused: Return 0.
Bits 15 to 0—Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting
value must be calculated as the following methods.
1. The operating frequency which is shown in MHz units must be rounded in a number to three
decimal places and be shown in a number of two decimal places.
2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ
parameter (general register R4). For example, when the operating frequency of the CPU is
28.882 MHz, the value is as follows.
1. The number to three decimal places of 28.882 is rounded and the value is thus 28.88.
2. The formula that 28.88 × 100 = 2888 is converted to the binary digit and
b'0000,1011,0100,1000 (H'0B48) is set to R4.
Rev.2.0, 07/03, page 757 of 960