SH7055S Datasheet, PDF (410/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Pø
TI10
AGCK
Noise
cancellation
period
Pφ × 10
(clock)
TCNT10H
NCR10
AGCK
operation
TCNT clock
External edge mask period
External edge mask period
0
1
0
1
Note: When rising and falling edges are set
Figure 11.27 Edge Input Operation (With Noise Cancellation)
Pø
TSTR
TST10
TCNT10A
Clock
AGCK
Capture
transfer
signal
TCNT reset
signal
ICR10A
00000001
TSR10
IMF10A
OCR10A
TSR10
CMF10A
00000002
00000003
12345677
1234
5678
00000001
55555555
55555556
55555557
00000000
12345678
Cleared by software
55555556
Cleared by software
Figure 11.28 TCNT10A Capture Operation and Compare-Match Operation
Internally synchronized AGCK is counted by event count 10B (TCNT10B), and when TCNT10B
reaches the value set beforehand in compare-match register 10B (OCR10B), a compare-match
occurs, and the compare-match trigger signal is transmitted to channel 0. By setting the
corresponding bit in TIER, an interrupt request can be sent to the CPU.
Rev.2.0, 07/03, page 372 of 960