SH7055S Datasheet, PDF (221/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

CK
Internal
address bus
Internal
data bus
SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2
SAR2 data
SAR2+2 data
SAR2+4 data
SAR2+6 data
SAR2 DAR2
SAR2 data
1st channel 2
transfer
SAR2 output
DAR2 output
2nd channel 2
transfer
3rd channel 2
transfer
4th channel 2
transfer
SAR2+2 output
DAR2 output
SAR2+4 output
DAR2 output
SAR2+6 output
DAR2 output
5th channel 2
transfer
SAR2 output
DAR2 output
After SAR2+6 output, SAR2 is reloaded
Bus right is returned one time in four
Figure 10.11 Source Address Reload Function Timing Chart
The reload function can be executed whether the transfer data size is 8, 16, or 32 bits.
DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every
single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore,
when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2.
Operation will not be guaranteed if any other value is set. Also, the counter which counts the
occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR
or the DE bit in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and
setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in
software standby mode, but SAR2, DAR2, DMATCR2, and other registers are not reset.
Consequently, when one of these sources occurs, there is a mixture of initialized counters and
uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in
this state. Therefore, when one of the above sources, other than TE setting, occurs during use of
the address reload function, SAR, DAR2, and DMATCR2 settings must be carried out before re-
execution.
10.3.10 DMA Transfer Ending Conditions
The DMA transfer ending conditions vary for individual channels ending and for all channels
ending together.
Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel’s DMA transfer count register (DMATCR) is 0, or when the DE bit of the
channel’s CHCR is cleared to 0.
Rev.2.0, 07/03, page 183 of 960