SH7055S Datasheet, PDF (714/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 9—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 8—PF4 Mode Bit (PF4MD): Selects the function of pin PF4/A20.
Bit 8:
PF4MD
0
1
Expanded Mode
with ROM Disabled
Address output (A20)
(Initial value)
Address output (A20)
Description
Expanded Mode
with ROM Enabled
General input/output (PF4)
(Initial value)
Address output (A20)
Single-Chip Mode
General input/output (PF4)
(Initial value)
General input/output (PF4)
• Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 6—PF3 Mode Bit (PF3MD): Selects the function of pin PF3/A19.
Bit 6:
PF3MD
0
1
Expanded Mode
with ROM Disabled
Address output (A19)
(Initial value)
Address output (A19)
Description
Expanded Mode
with ROM Enabled
General input/output (PF3)
(Initial value)
Address output (A19)
Single-Chip Mode
General input/output (PF3)
(Initial value)
General input/output (PF3)
• Bit 5—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 4—PF2 Mode Bit (PF2MD): Selects the function of pin PF2/A18.
Bit 4:
PF2MD
0
1
Expanded Mode
with ROM Disabled
Address output (A18)
(Initial value)
Address output (A18)
Description
Expanded Mode
with ROM Enabled
General input/output (PF2)
(Initial value)
Address output (A18)
Single-Chip Mode
General input/output (PF2)
(Initial value)
General input/output (PF2)
• Bit 3—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 2—PF1 Mode Bit (PF1MD): Selects the function of pin PF1/A17.
Bit 2:
PF1MD
0
1
Expanded Mode
with ROM Disabled
Address output (A17)
(Initial value)
Address output (A17)
Description
Expanded Mode
with ROM Enabled
General input/output (PF1)
(Initial value)
Address output (A17)
Single-Chip Mode
General input/output (PF1)
(Initial value)
General input/output (PF1)
Rev.2.0, 07/03, page 676 of 960