SH7055S Datasheet, PDF (197/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

10.1.3 Register Configuration
Table 10.1 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel
has four registers, and one overall DMAC control register is shared by all channels.
Table 10.1 DMAC Registers
Channel Name
0
DMA source
address register 0
DMA destination
address register 0
DMA transfer
count register 0
DMA channel
control register 0
1
DMA source
address register 1
DMA destination
address register 1
DMA transfer
count register 1
DMA channel
control register 1
2
DMA source
address register 2
DMA destination
address register 2
DMA transfer
count register 2
DMA channel
control register 2
Abbr.
SAR0
R/W
R/W
Initial
Value
Undefined
Address
Register Access
Size
Size
H'FFFFECC0 32 bits 16, 32*²
DAR0
R/W Undefined H'FFFFECC4 32 bits 16, 32*²
DMATCR0 R/W Undefined H'FFFFECC8 32 bits 16, 32*²
CHCR0 R/W*¹ H'00000000 H'FFFFECCC 32 bits 16, 32*²
SAR1
R/W Undefined H'FFFFECD0 32 bits 16, 32*²
DAR1
R/W Undefined H'FFFFECD4 32 bits 16, 32*²
DMATCR1 R/W Undefined H'FFFFECD8 32 bits 16, 32*³
CHCR1 R/W*¹ H'00000000 H'FFFFECDC 32 bits 16, 32*²
SAR2
R/W Undefined H'FFFFECE0 32 bits 16, 32*²
DAR2
R/W Undefined H'FFFFECE4 32 bits 16, 32*²
DMATCR2 R/W Undefined H'FFFFECE8 32 bits 16, 32*³
CHCR2 R/W*¹ H'00000000 H'FFFFECEC 32 bits 16, 32*²
Rev.2.0, 07/03, page 159 of 960