SH7055S Datasheet, PDF (592/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.3 Operation
The SH7055SF has an on-chip HCAN module with two channels, each of which can be controlled
independently. Except for pin states, both channels have identical specifications, and so control
should be carried out in the same way for both.
16.3.1 Hardware Reset and Software Reset
There are two ways of resetting the HCAN: Hardware reset and software reset.
Hardware Reset (Power-on Reset or Hardware/Software Standby): The MCR reset request bit
(MCR0) in MCR and the reset state bit (GSR3) in GSR within the HCAN are automatically set
and initialized (hardware reset). At the same time, all internal registers are initialized. However
mailbox (RAM) contents are not initialized. A flowchart of this reset is shown in figure 16.5.
Software Reset (Write to MCR0): In normal operation HCAN is initialized by setting the MCR
reset request bit (MCR0) in MCR (software reset). With this kind of reset, if the CAN controller is
performing a communication operation (transmission or reception), the initialization state is not
entered until the message has been completed. During initialization, the reset state bit (GSR3) in
GSR is set. In this kind of initialization, the error counters (TEC and REC) are initialized but other
registers and RAM are not. A flowchart of this reset is shown in figure 16.6.
Rev.2.0, 07/03, page 554 of 960