SH7055S Datasheet, PDF (83/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 2.10 Classification of Instructions (cont)
Operation
Classification Types Code
Function
No. of
Instructions
System
11
CLRT
T bit clear
31
control
CLRMAC MAC register clear
LDC
Load to control register
LDS
Load to system register
NOP
No operation
RTE
Return from exception processing
SETT
T bit set
SLEEP Transition to power-down mode
STC
Store control register data
STS
Store system register data
TRAPA Trap exception handling
Floating-point 15
FABS
Floating-point absolute value
22
instructions
FADD
Floating-point addition
FCMP Floating-point comparison
FDIV
Floating-point division
FLDI0
Floating-point load immediate 0
FLDI1
Floating-point load immediate 1
FLDS
Floating-point load into system register FPUL
FLOAT Integer-to-floating-point conversion
FMAC
Floating-point multiply-and-accumulate
operation
FMOV Floating-point data transfer
FMUL
Floating-point multiplication
FNEG Floating-point sign inversion
FSTS
Floating-point store from system register FPUL
FSUB
Floating-point subtraction
FTRC
Floating-point conversion with rounding to
integer
FPU-related 2
LDS
Load into floating-point system register
8
CPU
instructions
STS
Store from floating-point system register
Total: 79
172
Rev.2.0, 07/03, page 45 of 960