SH7055S Datasheet, PDF (462/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

12.2 Register Descriptions
12.2.1 Pulse Output Port Control Register (POPCR)
The pulse output port control register (POPCR) is a 16-bit readable/writable register.
POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
initialized in software standby mode.
Bit:
Initial value:
R/W:
15
PULS7
ROE
0
R/W
14
PULS6
ROE
0
R/W
13
PULS5
ROE
0
R/W
12
PULS4
ROE
0
R/W
11
PULS3
ROE
0
R/W
10
PULS2
ROE
0
R/W
9
PULS1
ROE
0
R/W
8
PULS0
ROE
0
R/W
Bit:
Initial value:
R/W:
7
PULS7
SOE
0
R/W
6
PULS6
SOE
0
R/W
5
PULS5
SOE
0
R/W
4
PULS4
SOE
0
R/W
3
PULS3
SOE
0
R/W
2
PULS2
SOE
0
R/W
1
PULS1
SOE
0
R/W
0
PULS0
SOE
0
R/W
• Bits 15 to 8—PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These bits
enable or disable 0 output to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 15 to 8:
PULS7ROE to PULS0ROE Description
0
0 output to APC pulse output pin (PULS7–PULS0) is disabled
(Initial value)
1
0 output to APC pulse output pin (PULS7–PULS0) is enabled
When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match
between the GR11B and TCNT11 values.
Rev.2.0, 07/03, page 424 of 960