SH7055S Datasheet, PDF (767/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

21.11.2 Port K Data Register (PKDR)
Bit: 15
14
13
12
11
10
9
8
PK15 PK14 PK13 PK12 PK11 PK10 PK9 PK8
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port K data register (PKDR) is a 16-bit readable/writable register that stores port K data. Bits
PK15DR to PK0DR correspond to pins PK15/TO8P to PK0/TO8A.
When a pin functions as a general output, if a value is written to PKDR, that value is output
directly from the pin, and if PKDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PKDR is read the pin state, not the register value, is
returned directly. If a value is written to PKDR, although that value is written into PKDR it does
not affect the pin state. Table 21.20 summarizes port K data register read/write operations.
PKDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Table 21.20 Port K Data Register (PKDR) Read/Write Operations
Bits 15 to 0:
PKIOR
Pin Function
0
General input
Other than
general input
1
General output
Other than
general output
Read
Pin state
Pin state
PKDR value
PKDR value
Write
Value is written to PKDR, but does not affect pin
state
Value is written to PKDR, but does not affect pin
state
Write value is output from pin
Value is written to PKDR, but does not affect pin
state
Rev.2.0, 07/03, page 729 of 960