SH7055S Datasheet, PDF (928/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

26.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing
Table 26.10 shows advanced timer unit timing and advanced pulse controller timing.
Table 26.10 Advanced Timer Unit Timing and Advanced Pulse Controller Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol Min
Max Unit
Output compare output delay time
Input capture input setup time
PULS output delay time
Timer clock input setup time
Timer clock pulse width (single edge
specified)
Timer clock pulse width (both edges
specified)
t
TOCD
t
TICS
t_PLSD
t_TCKS
t_TCKWH/L
t
TCKWH/L
—
100 ns
24*
—
ns
24 + t
cyc
–
100 ns
24*
—
ns
24 + t
cyc
3.0
—
t_cyc
5.0
—
t
cyc
Figures
Figure 26.12
Figure 26.13
[Operating precautions]
* The timer input signals and timer clock input signals are asynchronous, but judged to have
been changed at clock rise with two-state intervals shown in figures 26.12 and 26.13. If the
setup times shown here are not provided, recognition is delayed until the clock rise two states
after that timing.
Rev.2.0, 07/03, page 890 of 960