SH7055S Datasheet, PDF (930/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

26.3.6 I/O Port Timing
Table 26.11 shows I/O port timing.
Table 26.11 I/O Port Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ± 0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol
Min
Max
Unit
Port output data delay time
t
PWD
Port input hold time
t
PRH
Port input setup time
t_PRS
—
100
ns
24*
—
ns
24+tcyc
24*
—
ns
24+tcyc
Figures
Figure 26.14
[Operating precautions]
The port input signals are asynchronous, but judged to have been changed at CK clock rise with
two-state intervals shown in figure 26.14. If the setup times shown here are not provided,
recognition is delayed until the clock rise two states after that timing.
* The guaranteed operating range of power supply PV_CC1 in MCU single-chip mode is only
PV_CC1 = 5.0 V ±0.5 V. Do not use a voltage outside this range.
CK
Port
(read)
Port
(write)
t_PRS t_PRH
t_PWD
Figure 26.14 I/O Port Input/Output timing
Rev.2.0, 07/03, page 892 of 960