SH7055S Datasheet, PDF (381/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Output Compare Register 10B (OCR10B): Output compare register 10B (OCR10B) is an 8-bit
readable/writable register that is constantly compared with free-running counter 10B (TCNT10B).
When AGCK is input with both values matching, CMF10B in timer status register 10 (TSR10) is
set to 1.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
OCR10B is initialized to H'FF by a power-on reset, and in hardware standby mode and software
standby mode.
Reload Register 10C (RLD10C): Reload register 10C (RLD10C) is a 16-bit readable/writable
register. When STR10 in timer start register 1 (TSTR1) is 1 and RLDEN in the timer I/O control
register (TIOR10) is 0, and the value of TCNT10A is captured into input capture register 10A
(ICR10A), the ICR10A capture value is shifted according to the multiplication factor set by bits
PIM1 and PIM0 in TIOR10 before being transferred to RLD10C. The contents of reload register
10C (RLD10C) are loaded when reload counter 10C (TCNT10C) reaches H'0001.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
RLD10C is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
General Register 10G (GR10G): General register 10G (GR10G) is a 16-bit readable/writable
register with an output compare function. Function switching is performed by means of timer I/O
control register 10 (TIOR10). The GR10G value and free-running counter 10G (TCNT10G) value
are constantly compared, and when AGCK is input with both values matching, CMF10G in timer
status register 10 (TSR10) is set to 1.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
GR10G is initialized to H'FFFF by a power-on reset, and in hardware standby mode and software
standby mode.
Rev.2.0, 07/03, page 343 of 960