SH7055S Datasheet, PDF (42/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 1.1 SH7055SF Features (cont)
Item
Bus state
controller (BSC)
Direct memory
access controller
(DMAC)
(4 channels)
Advanced timer
unit-II (ATU-II)
Advanced pulse
controller (APC)
Features
• Supports external memory access (SRAM and ROM directly connectable)
 8/16-bit bus space
• 3.3 V bus interface
• 16 MB address space divided into four areas, with the following parameters
settable for each area:
 Bus size (8 or 16 bits)
 Number of wait cycles
 Chip select signals (CS0 to CS3) output for each area
• Wait cycles can be inserted using an external WAIT signal
• External access in minimum of two cycles
• Provision for idle cycle insertion to prevent bus collisions
• DMA transfer possible for the following devices:
 External memory, on-chip memory, on-chip peripheral modules
(excluding DMAC, UBC, BSC)
• DMA transfer requests by on-chip modules
 SCI, A/D converter, ATU-II, HCAN
• Cycle steal or burst mode transfer
• Dual address mode
 Direct transfer mode
 Indirect transfer mode (channel 3 only)
• Address reload function (channel 2 only)
• Transfer data width: Byte/word/longword
• Maximum 65 inputs or outputs can be processed
 Four 32-bit input capture inputs
 Thirty 16-bit input capture inputs/output compare outputs
 Sixteen 16-bit one-shot pulse outputs
 Eight 16-bit PWM outputs
 Six 8-bit event counters
 One gap detection function
• I/O pin output inversion function
• Maximum eight pulse outputs on reception of ATU-II (channel 11)
compare-match signal
Rev.2.0, 07/03, page 4 of 960