SH7055S Datasheet, PDF (106/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

3.4 Floating-Point Exception Model
3.4.1 Enable State Exceptions
Invalid operation and division-by-zero exceptions are both placed in the enable state by setting the
enable bit. All exceptions generated by the FPU are mapped as the same exception event. The
meaning of a particular exception is determined by software by reading system register FPSCR
and analyzing the information held there.
3.4.2 Disable State Exceptions
If the EV enable bit is not set, a qNaN will be generated as the result of an invalid operation
(except for FCMP and FTRC). If the EZ enable bit is not set, division-by-zero will return infinity
with the sign (+ or –) of the current expression. Overflow will generate a finite number which is
the largest value that can be expressed by an absolute value in the format, with the correct sign.
Underflow will generate zero with the correct sign. If the operation result is inexact, the
destination register will store that inexact result.
3.4.3 FPU Exception Event and Code
All FPU exceptions have a vector table address offset in address H'00000034 as the same general
exception event; that is, an FPU exception.
3.4.4 Floating-Point Data Arrangement in Memory
Single-precision floating-point data is located in memory at a 4-byte boundary; that is, it is
arranged in the same form as an SH7055SF long integer.
3.4.5 Arithmetic Operations Involving Special Operands
All arithmetic operations involving special operands (qNaN, sNaN, +INF, –INF, +0, –0) comply
with the specifications of the IEEE754 standard. Refer to the SH-2E Programming Manual for
details.
Rev.2.0, 07/03, page 68 of 960