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SH7055S Datasheet, PDF (608/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series
Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt
source settings and receive message specifications must be made. Interrupt source are set in the
mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). To receive a
message, the identifier must be set in advance in the message control (MCx[1] to MCx[8]) for the
receiving mailbox. When a message is received, all the bits in the receive message identifier are
compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox
0 (MC0[x], MD0[x]) has a local acceptance filter mask (LAFM) that allows Don’t Care settings to
be made.
1. CPU interrupt source settings
When transmitting, transmission acknowledge and transmission abort acknowledge interrupts
can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR).
When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt
register (IRR) interrupts can be masked in the interrupt mask register (IMR).
2. Arbitration field setting
In the arbitration field, the identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) of the
message to be received is set. If all the bits in the set identifier do not match, the message is
not stored in a mailbox.
Example: Mailbox 1
010_1010_1010 (standard identifier)
Only one kind of message identifier can be received by MB1
Identifier 1: 010_1010_1010
3. Local acceptance filter mask (LAFM) setting
The local acceptance filter mask is provided for mailbox 0 (MC0[x], MD0[x]) only, enabling a
Don’t Care specification to be made for all bits in the received identifier. This allows various
kinds of messages to be received.
Example: Mailbox 0
010_1010_1010 (standard identifier)
LAFM
000_0000_0011 (0: Care, 1: Don’t Care)
A total of four kinds of message identifiers can be received by MB0
Identifier 1: 010_1010_1000
Identifier 2: 010_1010_1001
Identifier 3: 010_1010_1010
Identifier 4: 010_1010_1011
Rev.2.0, 07/03, page 570 of 960