SH7055S Datasheet, PDF (411/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Figure 11.29 shows TCNT10B compare-match operation.
Pø
AGCK
TCNT10B
Clock
TCNT10B
00
01
OCR10B
TSR10
CMF10B
Channel 0
trigger
55
56
55
Cleared by software
Figure 11.29 TCNT10B Compare-Match Operation
Multiplied Clock Generation Function: The channel 10 16-bit reload counter (TCNT10C,
RLD10C) and 16-bit free-running counter 10G (TCNT10G) can be used to multiply the interval
between edges input from external pin TI10 by 32, 64, 128, or 256.
The value captured in ICR10A above is multiplied by 1/32, 1/64, 1/128, or 1/256 according to the
value set in the timer I/O control register (TIOR10), and transferred to the reload buffer
(RLD10C). At the same time, the same value is transferred to 16-bit reload counter 10C
(TCNT10C) and a down-count operation is started. When this counter reaches H'0001, the value is
read automatically from RLD10C and the down-count operation is repeated. When this reload
occurs, a multiplied clock signal (AGCK1) is generated. AGCK1 is converted to a corrected clock
(AGCKM) by the multiplied clock correction function described in the following section.
Channel 10 can also perform compare-match operation by means of the multiplied clock
(AGCK1) using general register 10G (GR10G) and 16-bit free-running counter 10G (TCNT10G).
TCNT10G is incremented unconditionally by AGCK1. By making the appropriate setting in the
interrupt enable register (TIER), an interrupt request can be sent to the CPU when TCNT10G and
GR10G match. The timing of this interrupt can be selected with the IREG bit in TIER as either on
occurrence of the compare-match or on input of the first TI10 edge after the compare-match.
TCNT10C operation is shown in figure 11.30, and TCNT10G compare-match operation in figure
11.31.
Rev.2.0, 07/03, page 373 of 960