SH7055S Datasheet, PDF (285/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 3—Clear Counter Enable Flag 3A, 4A, 5A, 3C, 4C, 5C (CCI3A, CCI4A, CCI5A, CCI3C,
CCI4C, CCI5C): These bits select enabling or disabling of free-running counter (TCNT)
clearing.
Bit 3: CCIxx
Description
0
TCNT clearing disabled
1
TCNT cleared on GR compare-match
xx = 3A, 4A, 5A, 3C, 4C, or 5C
(Initial value)
TCNT is cleared on compare-match only when GR is functioning as an output compare
register.
• Bits 2 to 0—I/O Control 3A2 to 3A0, 4A2 to 4A0, 5A2 to 5A0, 3C2 to 3C0, 4C2 to 4C0, 5C2
to 5C0 (IO3A2 to IO3A0, IO4A2 to IO4A0, IO5A2 to IO5A0, IO3C2 to IO3C0, IO4C2 to
IO4C0, IO5C2 to IO5C0): These bits select the general register (GR) function.
Bit 2:
IOxx2
0
1
Bit 1:
IOxx1
0
1
0
1
Bit 0:
IOxx0
0
1
0
1
0
1
0
1
xx = 3A, 4A, 5A, 3C, 4C, or 5C
Description
GR is an output
compare register
GR is an input
capture register
(input capture by
channel 3 and 9
compare-match
enabled)
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled (In channel 3
only, GR cannot be written to)
Input capture in GR on rising edge at
TIOxx pin (GR connot be written to)
Input capture in GR on falling edge at
TIOxx pin (GR connot be written to)
Input capture in GR on both rising and
falling edges at TIOxx pin (GR connot be
written to)
Rev.2.0, 07/03, page 247 of 960