SH7055S Datasheet, PDF (368/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Output Compare Registers 1 and 2A to 2H (OCR1, OCR2A to OCR2H)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The OCR registers are 16-bit readable/writable registers that have an output compare register
function.
The OCR and free-running counter (TCNT1B, TCNT2B) values are constantly compared, and if
the two values match, the CMF bit in the timer status register (TSR) is set to 1. If channels 1 and 2
and channel 8 are linked by the timer connection register (TCNR), the corresponding channel 8
down-counter (DCNT) is started at the same time.
The OCR registers can only be accessed by a word read.
The OCR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode
and software standby mode.
11.2.19 Input Capture Registers (ICR)
The input capture registers (ICR) are 32-bit registers. The ATU-II has four 32-bit ICR registers in
channel 0. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10
Registers.
Channel
0
Abbreviation
ICR0AH, ICR0AL,
ICR0BH, ICR0BL,
ICR0CH, ICR0CL,
ICR0DH, ICR0DL
Function
Dedicated input capture registers
Rev.2.0, 07/03, page 330 of 960