SH7055S Datasheet, PDF (505/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE
0
1
Description
Transmitter disabled
(Initial value)
The transmit data register empty bit (TDRE) in the serial status register
(SSR) is locked at 1.
Transmitter enabled
Serial transmission starts when the transmit data register empty (TDRE)
bit in the serial status register (SSR) is cleared to 0 after writing of
transmit data into TDR. Select the transmit format in SMR before setting
TE to 1.
• Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE
0
1
Description
Receiver disabled
(Initial value)
Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER,
ORER). These flags retain their previous values.
Receiver enabled
Serial reception starts when a start bit is detected in asynchronous
mode, or synchronous clock input is detected in synchronous mode.
Select the receive format in SMR before setting RE to 1.
Rev.2.0, 07/03, page 467 of 960