SH7055S Datasheet, PDF (287/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 3—Reserved: This bit is always read as 0. The write value should always be 0.
• Bits 2 to 0—I/O Control 11A2 to 11A0 (IO11A2 to IO11A0): These bits select the general
register (GR) function.
Bit 2:
IO11A2
0
1
Bit 1:
IO11A1
0
1
0
1
Bit 0:
IO11A0
0
1
0
1
0
1
0
1
Description
GR is an output
compare register
GR is an input
capture register
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge at
TIO11A pin (GR cannot be written to)
Input capture in GR on falling edge at
TIO11A pin (GR cannot be written to)
Input capture in GR on both rising and
falling edges at TIO11A pin (GR cannot
be written to)
11.2.5 Timer Status Registers (TSR)
The timer status registers (TSR) are 16-bit registers. The ATU-II has 11 TSR registers: one each
for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For
details of channel 10, see section 11.2.26, Channel 10 Registers.
Channel
0
1
2
3
4
5
6
7
8
9
11
Abbreviation
TSR0
TSR1A, TSR1B
TSR2A, TSR2B
TSR3
Function
Indicates input capture, interval interrupt, and overflow status
Indicate input capture, compare-match, and overflow status
Indicates input capture, compare-match, and overflow status
TSR6
TSR7
TSR8
TSR9
TSR11
Indicate cycle register compare-match status
Indicates down-counter output end (low) status
Indicates event counter compare-match status
Indicates input capture, compare-match, and overflow status
Rev.2.0, 07/03, page 249 of 960