SH7055S Datasheet, PDF (148/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

As indicated in table 7.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to
each register. Each of the corresponding interrupt priority ranks are established by setting a value
from H'0 (0000) to H'F (1111) in each of the four-bit groups 15–12, 11–8, 7–4, and 3–0. Interrupt
priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. If
multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1, DMAC2
and DMAC3, CMT0 and A/D0, and CMT1 and A/D1), those multiple modules are set to the same
priority rank.
IPRA–IPRL are initialized to H'0000 by a reset and in hardware standby mode. They are not
initialized in software standby mode.
7.3.2 Interrupt Control Register (ICR)
ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin
NMI and IRQ0 –IRQ7 and indicates the input signal level at the NMI pin. A reset and hardware
standby mode initialize ICR but the software standby mode does not.
Bit: 15
14
13
12
11
10
9
8
NMIL
—
—
—
—
—
—
NMIE
Initial value:
*
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S
Initial value:
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W
Note: * When NMI input is high: 1; when NMI input is low: 0
2
IRQ5S
0
R/W
1
IRQ6S
0
R/W
0
IRQ7S
0
R/W
• Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit
can be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL
0
1
Description
NMI input level is low
NMI input level is high
• Bits 14 to 9—Reserved: These bits always read 0. The write value should always be 0.
Rev.2.0, 07/03, page 110 of 960