SH7055S Datasheet, PDF (328/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 8—Input Capture/Compare-Match Interrupt Enable 4D (IME4D): Enables or disables
interrupt requests by IMF4D in TSR3 when IMF4D is set to 1.
Bit 8: IME4D
0
1
Description
IMI4D interrupt requested by IMF4D is disabled
IMI4D interrupt requested by IMF4D is enabled
(Initial value)
• Bit 7—Input Capture/Compare-Match Interrupt Enable 4C (IME4C): Enables or disables
interrupt requests by IMF4C in TSR3 when IMF4C is set to 1.
Bit 7: IME4C
0
1
Description
IMI4C interrupt requested by IMF4C is disabled
IMI4C interrupt requested by IMF4C is enabled
(Initial value)
• Bit 6—Input Capture/Compare-Match Interrupt Enable 4B (IME4B): Enables or disables
interrupt requests by IMF4B in TSR3 when IMF4B is set to 1.
Bit 6: IME4B
0
1
Description
IMI4B interrupt requested by IMF4B is disabled
IMI4B interrupt requested by IMF4B is enabled
(Initial value)
• Bit 5—Input Capture/Compare-Match Interrupt Enable 4A (IME4A): Enables or disables
interrupt requests by IMF4A in TSR3 when IMF4A is set to 1.
Bit 5: IME4A
0
1
Description
IMI4A interrupt requested by IMF4A is disabled
IMI4A interrupt requested by IMF4A is enabled
(Initial value)
• Bit 4—Overflow Interrupt Enable 3 (OVE3): Enables or disables interrupt requests by OVF3
in TSR3 when OVF3 is set to 1.
Bit 4: OVE3
0
1
Description
OVI3 interrupt requested by OVF3 is disabled
OVI3 interrupt requested by OVF3 is enabled
(Initial value)
Rev.2.0, 07/03, page 290 of 960