SH7055S Datasheet, PDF (308/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 2—Cycle Register Compare-Match Flag 6C/7C (CMF6C/CMF7C): Status flag that
indicates CYLRxC compare-match.
Bit 2: CMFxC
0
1
x = 6 or 7
Description
[Clearing condition]
(Initial value)
When CMFxC is read while set to 1, then 0 is written to CMFxC
[Setting conditions]
• When TCNTxC = CYLRxC (in non-complementary PWM mode)
• When TCNT6C = H'0000 in a down-count (in complementary PWM mode)
• Bit 1—Cycle Register Compare-Match Flag 6B/7B (CMF6B/CMF7B): Status flag that
indicates CYLRxB compare-match.
Bit 1: CMFxB
0
1
x = 6 or 7
Description
[Clearing condition]
(Initial value)
When CMFxB is read while set to 1, then 0 is written to CMFxB
[Setting conditions]
• When TCNTxB = CYLRxB (in non-complementary PWM mode)
• When TCNT6B = H'0000 in a down-count (in complementary PWM mode)
• Bit 0—Cycle Register Compare-Match Flag 6A/7A (CMF6A/CMF7A): Status flag that
indicates CYLRxA compare-match.
Bit 0: CMFxA
0
1
x = 6 or 7
Description
[Clearing condition]
(Initial value)
When CMFxA is read while set to 1, then 0 is written to CMFxA
[Setting conditions]
• When TCNTxA = CYLRxA (in non-complementary PWM mode)
• When TCNT6A = H'0000 in a down-count (in complementary PWM mode)
Rev.2.0, 07/03, page 270 of 960