SH7055S Datasheet, PDF (170/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Instruction fetch order:
Branch instruction fetch → next instruction overrun fetch →
overrun fetch of instruction after next → branch destination
instruction fetch
Instruction execution order: Branch instruction execution → branch destination instruction
execution
2. When branching with a delayed conditional branch instruction: BT/S and BF/S instructions
Instruction fetch order:
Branch instruction fetch → next instruction fetch (delay slot) →
overrun fetch of instruction after next → branch destination
instruction fetch
Instruction execution order: Branch instruction execution → delay slot instruction execution
→ branch destination instruction execution
Thus, when a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination instruction will be fetched after an overrun fetch of the next instruction or the
instruction after next. However, as the instruction that is the object of the break does not break
until fetching and execution of the instruction have been confirmed, the overrun fetches described
above do not become objects of a break.
If data accesses are also included as break conditions in addition to instruction fetch breaks, a
break will occur because the instruction overrun fetch is also regarded as satisfying the data break
condition.
8.5.3 Contention between User Break and Exception Processing
If a user break is set for the fetch of a particular instruction, and exception processing with higher
priority than a user break is in contention and is accepted in the decode stage for that instruction
(or the next instruction), user break exception processing may not be performed after completion
of the higher-priority exception service routine (on return by RTE).
Thus, if a user break condition is applied to the branch destination instruction fetch after a branch
(BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception processing),
and that branch instruction accepts exception processing with higher priority than a user break
interrupt, user break exception processing is not performed after completion of the higher-priority
exception service routine.
Therefore, a user break condition should not be set for the fetch of the branch destination
instruction after a branch.
8.5.4 Break at Non-Delay Branch Instruction Jump Destination
When a branch instruction with no delay slot (including exception processing) jumps to the jump
destination instruction on execution of the branch, a user break will not be generated even if a user
break condition has been set for the first jump destination instruction fetch.
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