SH7055S Datasheet, PDF (304/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 6—Input Capture/Compare-Match Flag 4B (IMF4B): Status flag that indicates GR4B input
capture or compare-match. The flag is not set in PWM mode.
Bit 6: IMF4B
0
1
Description
[Clearing condition]
(Initial value)
When IMF4B is read while set to 1, then 0 is written to IMF4B
[Setting conditions]
• When the TCNT4 value is transferred to GR4B by an input capture signal
while GR4B is functioning as an input capture register
• When TCNT4 = GR4B while GR4B is functioning as an output compare
register
• Bit 5—Input Capture/Compare-Match Flag 4A (IMF4A): Status flag that indicates GR4A
input capture or compare-match. The flag is not set in PWM mode.
Bit 5: IMF4A
0
1
Description
[Clearing condition]
(Initial value)
When IMF4A is read while set to 1, then 0 is written to IMF4A
[Setting conditions]
• When the TCNT4 value is transferred to GR4A by an input capture signal
while GR4A is functioning as an input capture register
• When TCNT4 = GR4A while GR4A is functioning as an output compare
register
• Bit 4—Overflow Flag 3 (OVF3): Status flag that indicates TCNT3 input capture or compare-
match.
Bit 4: OVF3
0
1
Description
[Clearing condition]
When OVF3 is read while set to 1, then 0 is written to OVF3
[Setting condition]
When the TCNT3 value overflows (from H'FFFF to H'0000)
(Initial value)
Rev.2.0, 07/03, page 266 of 960