SH7055S Datasheet, PDF (196/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Selectable bus modes: Cycle-steal mode or burst mode
• Fixed DMAC channel priority ranking
• CPU can be interrupted when the specified number of data transfers are complete.
10.1.2 Block Diagram
Figure 10.1 is a block diagram of the DMAC.
On-chip ROM
On-chip RAM
On-chip
peripheral
module
HCAN0
ATU-II
SCI0–SCI4
A/D converter 0–2
DEIn
DMAC module
Circuit
control
SARn
Register
control
DARn
Activation
control
DMATCRn
CHCRn
Request
priority
control
DMAOR
External
ROM
External
RAM
Bus interface
External I/O
(memory
mapped)
Bus state
controller
SARn: DMA source address register
DARn: DMA destination address register
DMATCRn: DMA transfer count register
CHCRn: DMA channel control register
DMAOR: DMA operation register
n: 0, 1, 2, 3
Figure 10.1 DMAC Block Diagram
Rev.2.0, 07/03, page 158 of 960