SH7055S Datasheet, PDF (939/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

26.3.12 AUD Timing
Table 26.17 shows AUD timing.
Table 26.17 AUD Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol Min
Max
Unit
AUDRST pulse width (Branch trace)
t
20
—
t
AUDRSTW
cyc
AUDRST pulse width (RAM monitor)
t
5
—
AUDRSTW
t
RMCYC
AUDMD setup time (Branch trace)
t_AUDMDS
20
—
t_cyc
AUDMD setup time (RAM monitor)
t_AUDMDS
5
—
t_RMCYC
Branch trace clock cycle
t_BTCYC
2
2
t_cyc
Branch trace clock duty
t
40
60
%
BTCKW
Branch trace data delay time
t
—
40
ns
BTDD
Branch trace data hold time
t
0
—
ns
BTDH
Branch trace SYNC delay time
t_BTSD
—
40
ns
Branch trace SYNC hold time
t_BTSH
0
—
ns
RAM monitor clock cycle
t
100
—
ns
RMCYC
RAM monitor clock low pulse width
t
45
—
ns
RMCKW
RAM monitor output data delay time
t
7
t – 20 ns
RMDD
RMCYC
RAM monitor output data hold time
t_RMDHD
5
—
ns
RAM monitor input data setup time
t_RMDS
20
—
ns
RAM monitor input data hold time
t
5
—
ns
RMDH
RAM monitor SYNC setup time
t
20
—
ns
RMSS
RAM monitor SYNC hold time
t
5
—
ns
RMSH
Load conditions: AUDCK (branch trace): CL = 30 pF: otherwise CL = 100 pF
AUDSYNC:
CL = 100 pF
AUDATA3 to AUDATA0: CL = 100 pF
Figures
Figure 26.24
Figure 26.25
Figure 26.26
Rev.2.0, 07/03, page 901 of 960