SH7055S Datasheet, PDF (765/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 21.18 Port J Data Register (PJDR) Read/Write Operations
Bits 15 to 0:
PJIOR
Pin Function
0
General input
Read
Pin state
Other than
general input
Pin state
1
General output PJDR value
Other than
PJDR value
general output
Write
Value is written to PJDR, but does not affect pin
state
Value is written to PJDR, but does not affect pin
state
Write value is output from pin
Value is written to PJDR, but does not affect pin
state
21.10.3 Port J Port Register (PJPR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PJ15 PJ14 PJ13 PJ12 PJ11 PJ10 PJ9 PJ8 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0
PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR
Initial value: * * * * * * * * * * * * * * * *
R/W: R R R R R R R R R R R R R R R R
Note: * The initial value is 1 when the PJ15 to PJ0 pins are high, and it is 0 when the pins are low.
The port J port register (PJPR) is a 16-bit read-only register that always stores the value of the port
J pins. The CPU cannot write data to this register. Bits PJ15PR to PJ0PR correspond to pins
PJ15/TI9F to PJ0/TIO2A. If PJPR is read, the corresponding pin values are returned.
• Bits 15 to 0: Port J15 to J0 Port Register (PJ15PR to PJ0PR)
PJ15PR to PJ0PR
0
1
Description
Low-level signals are output from or input to the PJ15 to PJ0 pins.
High-level signals are output from or input to the PJ15 to PJ0 pins.
Rev.2.0, 07/03, page 727 of 960