SH7055S Datasheet, PDF (452/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Contention between DCNT Write and Counter Clearing by Underflow: If an underflow
occurs in the T2 state of the channel 8 down-counter (DCNT8A to DCNT8P) write cycle by the
CPU, the DCNT continues counting down because the write to the DCNT by the CPU has
priority.
The timing in this case is shown in figure 11.72. In this example, a write of H'5555 to DCNT is
attempted at the same time as DCNT underflows.
Note: In the SH7055F, the retention of the H’0000 value has priority and the write to the DCNT
by the CPU is not performed. Note that the operation of the channel 8 down-counters
differs between SH7055SF and SH7055F.
T1
T2
Pøa
DCNT input clock
Address
DCNT address
Write data
5555
Internal write signal
Underflow signal
DCNT 0001
H'5555 is written to the DCNT because
the write to the DCNT has priority
0000
5555
Interrupt status flag
(OSF)
Figure 11.72 Contention between DCNT Write and Underflow
Rev.2.0, 07/03, page 414 of 960