SH7055S Datasheet, PDF (709/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

20.3.12 Port F IO Register (PFIOR)
Bit: 15
14
13
12
11
10
9
8
PF15 PF14 PF13 PF12 PF11 PF10 PF9
PF8
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port F. Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ to
PF0/A16. PFIOR is enabled when port F pins function as general input/output pins (PF15 to PF0),
and disabled otherwise.
When port F pins function as PF15 to PF0, a pin becomes an output when the corresponding bit in
PFIOR is set to 1, and an input when the bit is cleared to 0.
PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Rev.2.0, 07/03, page 671 of 960