SH7055S Datasheet, PDF (715/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 1—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 0—PF0 Mode Bit (PF0MD): Selects the function of pin PF0/A16.
Bit 0:
PF0MD
0
1
Expanded Mode
with ROM Disabled
Address output (A16)
(Initial value)
Address output (A16)
Description
Expanded Mode
with ROM Enabled
General input/output (PF0)
(Initial value)
Address output (A16)
Single-Chip Mode
General input/output (PF0)
(Initial value)
General input/output (PF0)
20.3.14 Port G IO Register (PGIOR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
— PG3IOR PG2IOR PG1IOR PG0IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
The port G IO register (PGIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 4 pins in port G. Bits PG3IOR to PG0IOR correspond to pins
PG3/IRQ3/ADTRG0 to PG0/PULS7/HRxD0/HRxD1.
When port G pins function as PG3 to PG0, a pin becomes an output when the corresponding bit in
PGIOR is set to 1, and an input when the bit is cleared to 0.
PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Rev.2.0, 07/03, page 677 of 960