SH7055S Datasheet, PDF (79/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 2.9 Instruction Formats (cont)
Instruction Formats
nm format
15
0
xxxx nnnn mmmm xxxx
md format
15
0
xxxx xxxx mmmm dddd
nd4 format
15
xxxx xxxx
0
nnnn dddd
Destination
Source Operand Operand
mmmm: Direct
register
nnnn: Direct
register
mmmm: Direct
register
nnnn: Indirect
register
mmmm: Indirect
post-increment
register (multiply-
and-accumulate)
MACH, MACL
nnnn*: Indirect
post-increment
register (multiply-
and-accumulate)
mmmm: Indirect
post-increment
register
nnnn: Direct
register
mmmm: Direct
register
nnnn: Indirect pre-
decrement
register
mmmm: Direct
register
nnnn: Indirect
indexed register
mmmmdddd:
Indirect register
with
displacement
R0 (Direct
register)
R0 (Direct
register)
nnnndddd:
Indirect register
with displacement
Example
ADD Rm,Rn
MOV.L Rm,@Rn
MAC.W
@Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L
Rm,@(R0,Rn)
MOV.B
@(disp,Rn),R0
MOV.B
R0,@(disp,Rn)
nmd format
15
0
xxxx nnnn mmmm dddd
mmmm: Direct
register
mmmmdddd:
Indirect register
with
displacement
nnnndddd: Indirect
register with
displacement
nnnn: Direct
register
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
Rev.2.0, 07/03, page 41 of 960