SH7055S Datasheet, PDF (470/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

13.1.2 Block Diagram
Figure 13.1 is the block diagram of the WDT.
ITI
(interrupt
signal)
Internal
reset signal*
Interrupt
control
Overflow
Reset
control
Clock
Clock
select
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal
clock sources
RSTCSR
TCNT
TCSR
Module bus
Bus
interface
WDT
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
Note: * The internal reset signal can be generated by making a register setting.
Figure 13.1 WDT Block Diagram
13.1.3 Pin Configuration
Table 13.1 shows the pin configuration.
Table 13.1 Pin Configuration
Pin
Abbreviation I/O
Watchdog timer overflow WDTOVF
O
Function
Outputs the counter overflow signal in
watchdog timer mode
Rev.2.0, 07/03, page 432 of 960