SH7055S Datasheet, PDF (191/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read
other external spaces, or for this chip, to perform write accesses. In the same manner, IW21 and
IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after
a CS1 space read, and IW01 and IW00, the number after a CS0 space read. 0 to 3 idle cycles can
be specified.
9.4.2 Simplification of Bus Cycle Start Detection
For consecutive accesses to the same CS space, waits are inserted to provide the number of idle
cycles designated by bits CW3 to CW0 in BCR2. However, in the case of a write cycle after a
read, the number of idle cycles inserted will be the larger of the two values designated by the IW
and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure
9.8 shows an example. A continuous access idle is specified for CSn space, and CSn space is
consecutively write-accessed.
T₁
T₂
T_idle
T₁
T₂
CK
Address
,
Data
CSn space access
Idle cycle
CSn space access
Figure 9.8 Same Space Consecutive Access Idle Cycle Insertion Example
Rev.2.0, 07/03, page 153 of 960