SH7055S Datasheet, PDF (184/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Bit 7:
W13
0
0
⋅⋅⋅
1
Bit 6:
W12
0
0
Bit 5:
W11
0
0
Bit 4:
W10
0
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
1
1
1
15 wait external wait input enabled
(Initial value)
• Bits 3–0—CS0 Space Wait Specification (W03, W02, W01, W00): These bits specify the
number of waits for CS0 space access.
Bit 3:
W03
0
0
⋅⋅⋅
1
Bit 2:
W02
0
0
Bit 1:
W01
0
0
Bit 0:
W00
0
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
1
1
1
15 wait external wait input enabled
(Initial value)
9.2.4 RAM Emulation Register (RAMER)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
— RAMS RAM2 RAM1 RAM0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM
area to be used when emulating realtime programming of flash memory.
RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Rev.2.0, 07/03, page 146 of 960