SH7055S Datasheet, PDF (141/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Source
Interrupt Vector
Vector Table
Vector Address
No. Offset
Interrupt
Priority
(Initial
Value)
Priority
Corre- within IPR
sponding Setting
IPR (Bits) Range
ATU2 ATU21 IMI2A/C 108 H'000001B0 to 0 to 15 (0) IPRE
↑
1
MI2A
H'000001B3
(11–8)
IMI2B/C 109 H'000001B4 to
2
MI2B
H'000001B7
IMI2C/C 110 H'000001B8 to
3
MI2C
H'000001BB
IMI2D/C 111
MI2D
H'000001BC
to H'000001BF
↓
4
ATU22 IMI2E/C 112
MI2E
H'000001C0 to 0 to 15 (0) IPRE
H'000001C3
(7–4)
↑
1
IMI2F/C 113 H'000001C4 to
2
MI2F
H'000001C7
IMI2G/C 114 H'000001C8 to
3
MI2G
H'000001CB
IMI2H/C 115
MI2H
H'000001CC
to H'000001CF
↓
4
ATU23 OVI2A/O 116
VI2B
H'000001D0 to 0 to 15 (0) IPRE
H'000001D3
(3–0)
ATU3 ATU31 IMI3A 120 H'000001E0 to 0 to 15 (0) IPRF
↑
1
H'000001E3
(15–12)
IMI3B 121 H'000001E4 to
2
H'000001E7
IMI3C 122 H'000001E8 to
3
H'000001EB
IMI3D 123
H'000001EC
to H'000001EF
↓
4
ATU32 OVI3 124 H'000001F0 to 0 to 15 (0) IPRF
H'000001F3
(11–8)
Default
Priority
High
Low
Rev.2.0, 07/03, page 103 of 960