SH7055S Datasheet, PDF (576/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.2.10 Remote Request Register (RFPR)
The remote request register (RFPR) is a 16-bit readable/writable register containing status flags
that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register
is set, the corresponding bit in the receive complete register (RXPR) is also set.
Bit: 15
14
13
12
11
10
9
8
RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 15 to 0—Remote Request Register (RFPR7 to 0, RFPR15 to 8): These bits indicate that a
remote frame has been received normally in the corresponding mailbox.
Bit x: RFPRx
0
1
Description
[Clearing condition]
Writing 1
(Initial value)
Completion of remote frame reception in corresponding mailbox
16.2.11 Interrupt Register (IRR)
The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the
various interrupt sources.
Bit:
Initial value:
R/W:
15
IRR7
0
R/W
14
IRR6
0
R/W
13
IRR5
0
R/W
12
IRR4
0
R/W
11
IRR3
0
R/W
10
IRR2
0
R
9
IRR1
0
R
8
IRR0
1
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
— IRR12 —
—
IRR9 IRR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R
R
R
R/W
Rev.2.0, 07/03, page 538 of 960