SH7055S Datasheet, PDF (305/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 3—Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR5D
input capture or compare-match.
Bit 3: IMF3D
0
1
Description
[Clearing condition]
(Initial value)
When IMF3D is read while set to 1, then 0 is written to IMF3D
[Setting conditions]
• When the TCNT3 value is transferred to GR3D by an input capture signal
while GR3D is functioning as an input capture register. However, IMF3D
is not set by input capture with a channel 9 compare match as the trigger
• When TCNT3 = GR3D while GR3D is functioning as an output compare
register
• When TCNT3 = GR3D while GR3D is functioning as a synchronous
register in PWM mode
• Bit 2—Input Capture/Compare-Match Flag 3C (IMF3C): Status flag that indicates GR3C input
capture or compare-match. The flag is not set in PWM mode.
Bit 2: IMF3C
0
1
Description
[Clearing condition]
(Initial value)
When IMF3C is read while set to 1, then 0 is written to IMF3C
[Setting conditions]
• When the TCNT3 value is transferred to GR3C by an input capture signal
while GR3C is functioning as an input capture register. However, IMF3C
is not set by input capture with a channel 9 compare match as the trigger
• When TCNT3 = GR3C while GR3C is functioning as an output compare
register
• Bit 1—Input Capture/Compare-Match Flag 3B (IMF3B): Status flag that indicates GR3B input
capture or compare-match. The flag is not set in PWM mode.
Bit 1: IMF3B
0
1
Description
[Clearing condition]
(Initial value)
When IMF3B is read while set to 1, then 0 is written to IMF3B
[Setting conditions]
• When the TCNT3 value is transferred to GR3B by an input capture signal
while GR3B is functioning as an input capture register. However, IMF3B is
not set by input capture with a channel 9 compare match as the trigger
• When TCNT3 = GR3B while GR3B is functioning as an output compare
register
Rev.2.0, 07/03, page 267 of 960